1. Field of the Invention
The present invention relates to a cell for a shift register. It is especially useful in methods for testing the operation of applications specific integrated circuits.
Applications specific integrated circuits (ASIC) are integrated circuits made on a single chip at the user's request. Certain applications specific integrated circuits have a central processing unit (for example a dedicated signal processor or DSP in the case of an integrated circuit dedicated to signal processing) associated with a certain number of devices that depends on the application of the circuit: memories, interfaces, etc.
The user gives the manufacturer the application program of the circuit and information on the desired circuit configuration such as the type and volume of the memories or the nature of the interface devices of the circuit. The integrated circuit is then made on a chip by associating specific devices with the central processing unit, these specific devices being notably a read-only memory (ROM) containing the application program.
For the manufacturer's test, there is a known way of making the central processing unit carry out an automatic testing program stored in the program memory of the circuit. Since the configurations depend on the user's request, it is not possible to plan for a single testing program.
To test integrated circuits, there is also a known way, described for example in EP-0 358 376, of using a shift register formed by the series connection of a set of elementary cells mounted on the input/output lines of the integrated circuit. Each cell can carry out the injection, on its respective line, of a value introduced serially through the shift register, and sample the value of the signal conveyed by this line with a view to a serial reading through the shift register. It is thus possible to inject test signals into the integrated circuit and check the behavior of the circuit in response to these signals.
One drawback of this system is that it does not enable direct access to the internal buses of the circuit used for communications between the central processing unit and the devices depending on the application, unless the number of cells is considerably increased. This adversely affects the compactness of the circuit and the speed of the shift register.
There is a known way, described for example in EP-0 578 540, of using a shift register formed by connecting cells mounted on the input/output lines of the central processing unit. This makes it possible to test both the central processing unit and the associated devices with a small number of cells. It also enables the testing of a large number of possible configurations without modifying the shift register.
Typically, a cell used to take position in a shift register is series-connected on a line (a line providing access to a central processing unit for example) and series-connected with other cells connected to other lines. Physically, said line will therefore be separated into two parts. For example, if such a cell is mounted on a line of a bus between a central processing unit and a peripheral, a part of the line will go from the central processing unit to the cell and tile other part of the line will go from the cell to the peripheral. A cell such as this therefore has an input, called a parallel input, connected to one part of the line, an output, called a parallel output, connected to the other part of the line (for the injection, into this part of the line, of a value transmitted from the exterior through the other cells or in order to give the value present at the parallel input, in which case the cell is transparent), a series input and a series output to enable the gradual shifting, in the shift register in which the cell is placed, of the values to be injected or the sampled values.
It can therefore be seen that the cells could be one-directional if they are mounted on lines having one defined direction of signal propagation or bi-directional if they are mounted on lines used to transmit signals in both directions, in which case the parallel inputs and outputs are actually inputs/outputs.
Typically, the one-directional cells have a memorization or storage flip-flop (for example a master-slave type of delay circuit) capable of receiving, at input, either the value of the signal present at the parallel input (in the case of a sampling), or at the series input (in the case of an injection or a shift), the output of this storage flip-flop being connected to the series output (to enable the shift from one cell to the other). Furthermore, the one-directional circuit also comprise, conventionally, a multiplexer having one input connected to the parallel input and one input connected to the output of the storage flip-flop, if necessary by a latch and an output connected to the parallel output, this multiplexer enabling the injection of a value into the line or making it possible to render the cell transparent to the line (the parallel input and output being then connected). These different means are controlled by command signals coming either from an external control block or from an internal control block receiving external command signals, the test procedures being of course controlled from outside the circuit.
In the case of the bidirectional cells, the composition of the cells is identical except that they include an additional multiplexer having one input connected to the parallel output (which behaves as an input/output), one input connected to the output of the storage flip-flop (possibly by a latch) and one output connected to the parallel input (which behaves as an input/output). Furthermore, it is necessary to provide for a command and an additional input in the multiplexing means needed to enable the giving, at the input of the storage flip-flop, of either the value of the signal present at the series input (in the event of a shift) or the value of one of the signals present at the parallel input and output (in the event of sampling).
The cells conventionally used have several drawbacks:
they induce delays, of 0.5 to 2 nanoseconds depending on the technology used, in the propagation of a signal in the line, owing to the crossing of at least one multiplexer, PA1 they raise a problem of synchronization inasmuch as the signals present in the lines depend on clocks internal to the circuit while the command signals of a shift register used to shift sampled values depend on a clock external to the circuits since, in practice, the values to be injected or the values sampled are given by or to testing devices external to the circuits to be tested. This therefore makes it necessary either to produce shift command signals from signals external to the circuit, which are synchronized with the internal clock signals, or to stop the internal clock signals so as to ensure the stability of the values of the signals present at the lines when it is desired to sample them. The first approach has the drawback of requiring additional resources and hence of increasing the size and power consumption of the circuits while the second approach has the drawback of making it necessary to interrupt the operation of the circuits at each sampling operation, PA1 they do not guarantee the internal logic state of the cell, for example the cell present at the output of the storage flip-flop where possible leaks may as the case may be cause deterioration in this signal, there being no loop designed to hold this signal, PA1 they raise a problem of consumption at the input of the storage flip-flops or latches, when these circuits are off (input insulated from the output), for they are then insulated and may be subject to capacitive or dynamic type leaks for example at the substrates of input transistors. PA1 a parallel input connected to the line to receive a parallel input signal, PA1 a parallel output connected to the line to give a parallel output signal, PA1 a series input to receive a series input signal to be shifted into a following cell or to be injected into the line, PA1 a series output to give a series output signal to a series input of a following cell, PA1 wherein the parallel input and the parallel output are connected and wherein the parallel output is separated from the rest of the cell by a tristate buffer circuit.